Conventional thin silicon PIN detectors are typically fabricated from a bulk wafer, i.e., a wafer having a thickness dimension between approximately 150–200 microns. On a front surface of the wafer, detectors are fabricated using semiconductor lithographic and thinfilm techniques. The backside of the wafer is implanted to form the second field plate of the detector. These wafers are then diced and hybridized onto individual readout integrated circuits (ROICs). A wirebond contact is made to the implanted field plate or detector common.
Prior attempts to process thin PIN detectors include, for example, processing the PIN detector as a thick wafer, for example 150–200 microns, and then mechanically thinning and implanting components at the detector level.
One conventional semiconductor device of silicon-on-insulator (SOI) complementary metal-oxide semiconductor (CMOS) is disclosed in U.S. Pat. No. 5,137,837, entitled, “Radiation-Hard, High-Voltage Semiconductive Device Structure Fabricated on SOI Substrate”, issued Aug. 11, 1992 to Chen-Chi P. Chang et al. This semiconductor device includes highly-doped buried n-type and p-type wells in a first silicon layer, which covers an insulator, and over which a second silicon layer is formed with congruent lightly-doped n-type and p-type layers in which complementary MOSFET active devices are formed. While the semiconductor device formed by this process has many advantages, one drawback is that two separate silicon formation steps are required.
Another conventional CMOS device is disclosed in U.S. Pat. No. 5,807,771, entitled, “Radiation-Hard, Low Power, Submicron CMOS on a SOI Substrate”, issued Sep. 15, 1998 to Truc Q. Vu et al. This patent relates to a radiation-hard, low-power semiconductor device of the CMOS type that is fabricated with a sub-micron feature size on a silicon-on-insulator (SOI) substrate. The SOI substrate may be of several different types.
Yet another conventional detector device is disclosed in U.S. Pat. No. 4,782,028, entitled, “Process Methodology for Two-Sided Fabrication of Devices on Thinned Silicon” issued Nov. 1, 1998 to Michael G. Farrier et al. This patent relates to a method for forming a detector device, such as a thinned bulk silicon blocked impurity transducer infrared detector, by thinning a semiconductor substrate and processing the thinned region on two sides to form the detector device. The semiconductor substrate is thinned to form a cavity in the substrate. Further processing on both sides of the thinned region is performed while the thinned region is still connected to the thicker substrate. The thinned region is then separated from the substrate upon completion of the processing steps. The device is then mounted to a readout device.